1. Field of the Invention
The present invention relates to a computer program that a user can use via a computer system, and that assists human users for LSI test flow generation.
2. Description of the Related Art
At a generation of a test flow, conventionally, a flow of a test which is applied to detect manufacturing defects was generated with fumbling, without concrete criteria, based only on knowledge and experience. Explaining about a test to detect manufacturing defects, at LSI production, a test is applied in order to detect defects occurring on a manufacturing process. As an example, a signal wire may short-circuit or be opened due to a small particle during manufacturing, and thus such a badly-affected device has to be detected as defective.
For recent highly-integrated LSIs, faults are not always efficiently detected if only test patterns for functional verification is applied to a target circuit as that being implemented by a designer. Therefore, it is required to modify the circuit based on design-for-testability (DFT) techniques, and then to generate appropriate test patterns. This sequence of DFT application and test pattern generation is referred to as a test flow. Generation of a test flow was done with fumbling, without concrete criteria, based only on knowledge and experience.
However, for the generation of a test flow which is done with fumbling without concrete criteria based only on knowledge and experience, a mistake of an engineer can occur, or different engineer might differently determine, and thus inconvenience might occur such as: redundantly increased LSI circuit overhead due to inclusion of unnecessary test into a test flow, increased test cost due to increased number of test patterns, yield loss (increased manufacturing cost per a good chip) due to inability to correctly identify good and defective devices, and increased field failure (degraded reliability).
If a necessary test is not included, defective chips might be shipped. If unnecessary test is included in a test flow, potentially good device might sometimes be misjudged as defective. A possible cause of misjudge for good device as defective is, for example, that a pattern is generated targeting a path which should not be tested. In particular, by a scan circuit, a device can make a transition into a specific state to which the device cannot reach under normal operation, and then a test might be applied under such a state. In other cases, since activity of a circuit during a test sometimes goes higher (that is, a device is fluttering all over) than for normal operation, some devices may slow down due to electric power shortage only at the test, and thus a part of the devices may underperform a specification due to joint effect with process variation.
If a test flow has to be re-generate, it could lead to inconvenience of increased turnaround time for design and development. Therefore, it is hoped that even inexperienced engineer can easily generate adequate test flow for a given target LSI device.
The Japanese Unexamined Patent Application Publication No. 2006-31354 discloses a technique about LSI production test.
A problem that the present invention intend to resolve is to realize a generation of a test flow without relying on an engineer's knowledge and experience, where a generated test flow includes a test required to correctly identify a good device as good and a bad device as bad, while excluding any unnecessary test.
In particular, although a generated test flow is not guaranteed as mathematically optimum, it is an intention of the present invention that an automated generation of a test flow is realized, where the generated test flow contributes to reduction of turnaround time for design and development (that is, much less than manual generation), reduction of manufacturing cost and test cost, and improvement of reliability of manufactured LSIs.